VEEK-MT2 Board
It consists of a DE2-115 board front panel and a rear 800x480 pixel color LCD module.
Contain device: EP4CE115F29C7
Family Cyclone IV E Package FBGA Pin count
780 Speed grade 7
Parameters: 114480 logic elements, 3888 kbit embedded memory, 266 hardware multipliers 18x18 bits, 4 PLLs, and 528 user pins.
Picture overview of basic I/O of front DE2-115 board: 1500 x 1000 750 x 500
Important note: The board requires a power supply =12 V.
Always check that you use the correct one !!!
Beginners should utilize the ready-made default project below and can take inspiration from the DCE library.
See the Guides page if you would prefer to create a Quartus project from scratch.
Optional Documents
- VEEK-MT2_v.1.0.2_SystemCD.zip - (90 MB) - CD supplied with the board.
- VEEK-MT2_User_Manual.pdf - extract for the System CD.
- DE2_115_control_panel.zip - also works for VEEK-MT2. The panel is included in the System CD and in the DCE library zip above.
1.
By Quartus programmer, load win7_64bits\DE2_115_ControlPanel.sof (SRAM Object File) into the Veek-MT2 board.|
2. In Windows, run win7_64bits\DE2_115_ControlPanel.exe. We tested it only on Windows 7 and 10.
- DE2-115_SystemCD.zip - (191 MB) CD supplied with the DE115 board (the front part of Veek-MT2).
- DE2_115_User_manual.pdf - user manual with a detailed description of DE2-115 board, the extracted from the DE115 system CD.
- My_First_Fpga.pdf - comprehensive information that will help you understand how to create
a FPGA design on you DE2-115 development board.
- My_First_Niosii.pdf
- how to create an FPGA-based SOPC (System-On-a-Programmable-Chip) with soft-core microprocessor NIOS
and run software upon it.
LSP lectures will mention this highly advanced part and also RISC-V processor, but unfortunately,
they don't have enough time for FPGA applications of soft-core processors in practical exercises.